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Adat/hardware/rev0/adatface_baseboard.kicad_dru
2026-03-13 19:58:28 +03:00

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(version 1)
# 4-layer, 1oz copper
# In global rules
#(rule "Minimum Trace Width and Spacing (outer layer)"
# (constraint track_width (min 3.5mil))
# (constraint clearance (min 3.5mil))
# (layer outer)
# (condition "A.Type == 'track' && B.Type != 'Zone'"))
(rule "Minimum Trace Width and Spacing (inner layer)"
(constraint track_width (min 5mil))
(constraint clearance (min 5mil))
(layer inner)
(condition "A.Type == 'track' && B.Type != 'Zone'"))
# silkscreen
# This is just JLCPCB being overly cautious, <6mil is readable.
#(rule "Minimum line width"
# (constraint track_width (min 6mil))
# (layer "F.Silkscreen") (layer "B.Silkscreen"))
(rule "Pad to Silkscreen"
(constraint clearance (min 0.15mm))
(layer outer)
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
# edge clearance
# in global rules
#(rule "Trace to Outline"
# (constraint edge_clearance (min 0.2mm))
# (condition "A.Type == 'track'"))
# drill/hole size
# in global rules
#(rule "drill hole size (mechanical)"
# (constraint hole (min 0.2mm) (max 6.3mm))
# (condition "A.Type == 'hole'"))
#
#(rule "Minimum Via Hole Size"
# (constraint hole (min 0.2mm))
# (condition "A.Type == 'via'"))
#
#(rule "Minimum Via Diameter"
# (constraint length (min 0.4mm))
# (condition "A.Type == 'via' && Lay"))
# JLCPCB's guidelines here are contradictory; they say that PTH hole size minimum is .2,
# then they immediately after that they say that the pad has to be 1mm in size with a minimum .5mm hole size?
# At first they say that the minimum PTH annular width is .15, but then they say it's .25?
# this is very confusing, we'll just go with the smaller number.
(rule "PTH Hole Size"
(constraint hole (min 0.2mm) )
(condition "A.isPlated() && A.Type != 'via'"))
(rule "PTH Annular Width"
(constraint annular_width (min 0.15mm) )
(condition "A.isPlated() && A.Type != 'via'"))
(rule "Minimum Non-plated Hole Size"
(constraint hole (min 0.5mm))
(condition "A.Type == 'pad' && !A.isPlated()"))
# clearance
(rule "via to track clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'track'"))
(rule "via to via clearance (same nets)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'via' && B.Type == 'via' && A.Net == B.Net"))
(rule "pad to pad clearance (with hole, different nets)"
(constraint hole_clearance (min 0.5mm))
(condition "A.Type == 'through-hole' && B.Type == A.Type && A.Net != B.Net"))
(rule "pad to pad clearance (without hole, different nets)"
(constraint clearance (min 0.127mm))
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
(rule "NPTH to Track clearance)"
(constraint hole_clearance (min 0.254mm))
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
(rule "PTH to Track clearance)"
(constraint hole_clearance (min 0.33mm))
(condition "A.isPlated() && B.Type == 'track'"))
#Only non-via pads
(rule "Pad to Track clearance)"
(constraint clearance (min 0.2mm))
(condition "A.isPlated() && A.type != 'via' && B.Type == 'track'"))