134 lines
5.8 KiB
Python
134 lines
5.8 KiB
Python
from amaranth import *
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from amaranth.build import *
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from amaranth_boards.resources import *
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from amaranth_boards.qmtech_ep4ce import QMTechEP4CEPlatform
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from amaranth_boards.qmtech_5cefa2 import QMTech5CEFA2Platform
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from amaranth_boards.qmtech_10cl006 import QMTech10CL006Platform
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from amaranth_boards.qmtech_xc7a35t import QMTechXC7A35TPlatform
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from amaranth_boards.colorlight_qmtech import ColorlightQMTechPlatform
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from luna.gateware.platform.core import LUNAPlatform
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from car import ColorlightDomainGenerator, IntelCycloneIVClockDomainGenerator, IntelCycloneVClockDomainGenerator, Xilinx7SeriesClockDomainGenerator
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from adatface_rev0_baseboard import ADATFaceRev0Baseboard
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class IntelFPGAParameters:
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QSF_ADDITIONS = r"""
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set_global_assignment -name OPTIMIZATION_MODE "Aggressive Performance"
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set_global_assignment -name FITTER_EFFORT "Standard Fit"
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT "Extra"
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set_instance_assignment -name DECREASE_INPUT_DELAY_TO_INPUT_REGISTER OFF -to *ulpi*
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set_instance_assignment -name INCREASE_DELAY_TO_OUTPUT_PIN OFF -to *ulpi*
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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"""
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SDC_ADDITIONS = r"""
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derive_pll_clocks
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derive_clock_uncertainty
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# sync clock domain crossing to ADAT clock domain crossing
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set_max_delay -from [get_clocks {car|audiopll|auto_generated|pll1|clk[3]}] -to [get_clocks {car|audiopll|auto_generated|pll1|clk[0]}] 5
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# USB to fast clock domain crossing
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set_max_delay -from [get_clocks {car|mainpll|auto_generated|pll1|clk[0]}] -to [get_clocks {car|fastopll|auto_generated|pll1|clk[0]}] 5
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"""
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class ADATFaceCycloneV(QMTech5CEFA2Platform, LUNAPlatform):
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fast_multiplier = 9
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clock_domain_generator = IntelCycloneVClockDomainGenerator
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fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
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@property
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def file_templates(self):
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templates = super().file_templates
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templates["{{name}}.qsf"] += IntelFPGAParameters.QSF_ADDITIONS
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templates["{{name}}.sdc"] += IntelFPGAParameters.SDC_ADDITIONS
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return templates
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def __init__(self):
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self.resources += ADATFaceRev0Baseboard.resources(Attrs(io_standard="3.3-V LVCMOS"))
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# swap connector numbers, because on ADATface the connector
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# names are swapped compared to the QMTech daughterboard
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self.connectors[0].number = 3
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self.connectors[1].number = 2
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super().__init__(standalone=False)
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class ADATFaceCycloneIV(QMTechEP4CEPlatform, LUNAPlatform):
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fast_multiplier = 9
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clock_domain_generator = IntelCycloneIVClockDomainGenerator
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fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
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@property
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def file_templates(self):
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templates = super().file_templates
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templates["{{name}}.qsf"] += IntelFPGAParameters.QSF_ADDITIONS
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templates["{{name}}.sdc"] += IntelFPGAParameters.SDC_ADDITIONS
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return templates
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def __init__(self):
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self.resources += ADATFaceRev0Baseboard.resources(Attrs(io_standard="3.3-V LVCMOS"))
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# swap connector numbers, because on ADATface the connector
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# names are swapped compared to the QMTech daughterboard
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self.connectors[0].number = 3
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self.connectors[1].number = 2
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super().__init__(no_kluts=55, standalone=False)
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# This is here just for experimental reasons.
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# right now the design probably would not fit into this device anymore
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class ADATFaceCyclone10(QMTech10CL006Platform, LUNAPlatform):
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clock_domain_generator = IntelCycloneIVClockDomainGenerator
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fast_multiplier = 9
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fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
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@property
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def file_templates(self):
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templates = super().file_templates
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templates["{{name}}.qsf"] += IntelFPGAParameters.QSF_ADDITIONS
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templates["{{name}}.sdc"] += IntelFPGAParameters.SDC_ADDITIONS
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return templates
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def __init__(self):
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self.resources += ADATFaceRev0Baseboard.resources(Attrs(io_standard="3.3-V LVCMOS"))
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# swap connector numbers, because on ADATface the connector
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# names are swapped compared to the QMTech daughterboard
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self.connectors[0].number = 3
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self.connectors[1].number = 2
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super().__init__(standalone=False)
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class ADATFaceArtix7(QMTechXC7A35TPlatform, LUNAPlatform):
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clock_domain_generator = Xilinx7SeriesClockDomainGenerator
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fast_multiplier = 9
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fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
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@property
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def file_templates(self):
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templates = super().file_templates
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return templates
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def __init__(self):
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self.resources += ADATFaceRev0Baseboard.resources(Attrs(IOSTANDARD="LVCMOS33"))
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# swap connector numbers, because on ADATface the connector
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# names are swapped compared to the QMTech daughterboard
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self.connectors[0].number = 3
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self.connectors[1].number = 2
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super().__init__(standalone=False)
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class ADATFaceColorlight(ColorlightQMTechPlatform, LUNAPlatform):
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clock_domain_generator = ColorlightDomainGenerator
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fast_domain_clock_freq = ColorlightDomainGenerator.FastClockFreq
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@property
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def file_templates(self):
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templates = super().file_templates
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return templates
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def __init__(self):
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adatface_resources = ADATFaceRev0Baseboard.resources(Attrs(IO_TYPE="LVCMOS33"), colorlight=True)
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# swap connector numbers, because on ADATface the connector
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# names are swapped compared to the QMTech daughterboard
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self.connectors[0].number = 3
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self.connectors[1].number = 2
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from amaranth_boards.colorlight_i9 import ColorLightI9Platform
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super().__init__(colorlight=ColorLightI9Platform, daughterboard=False, extra_resources=adatface_resources) |