234 lines
9.2 KiB
Python
234 lines
9.2 KiB
Python
from amaranth import *
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from amaranth.build import Platform
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from amaranth.lib.fifo import SyncFIFO
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from amlib.stream import StreamInterface, connect_stream_to_fifo
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from amlib.test import GatewareTestCase, sync_test_case
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class BundleMultiplexer(Elaboratable):
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NO_CHANNELS_ADAT = 8
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SAMPLE_WIDTH = 24
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FIFO_DEPTH = 32 * NO_CHANNELS_ADAT
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def __init__(self, no_bundles=4):
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# parameters
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self._no_bundles = no_bundles
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self._channel_bits = Shape.cast(range(no_bundles * self.NO_CHANNELS_ADAT)).width
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self._bundle_channel_bits = Shape.cast(range(self.NO_CHANNELS_ADAT)).width
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# ports
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self.channel_stream_out = StreamInterface(name="channel_stream",
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payload_width=self.SAMPLE_WIDTH,
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extra_fields=[("channel_nr", self._channel_bits)])
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self.bundles_in = Array(StreamInterface(name=f"input_bundle{i}",
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payload_width=self.SAMPLE_WIDTH,
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extra_fields=[("channel_nr", self._bundle_channel_bits)])
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for i in range(no_bundles))
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self.bundle_active_in = Array(Signal(name=f"bundle{i}_active") for i in range(no_bundles))
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self.no_channels_in = Array(Signal(self._bundle_channel_bits + 1, name=f"no_channels{i}") for i in range(no_bundles))
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# debug ports
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self.current_bundle = Signal(range(no_bundles))
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self.last_bundle = Signal()
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self.levels = Array(Signal(5, name=f"rx{i}_fifo_level") for i in range(1,5))
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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sample_width = self.SAMPLE_WIDTH
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bundle_bits = self._bundle_channel_bits
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bundle_ready = Array(Signal( name=f"bundle{i}_ready") for i in range(self._no_bundles))
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bundle_sample = Array(Signal(sample_width, name=f"bundle{i}_sample") for i in range(self._no_bundles))
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bundle_channel = Array(Signal(bundle_bits, name=f"bundle{i}_channel") for i in range(self._no_bundles))
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last = Array(Signal( name=f"bundle{i}_last") for i in range(self._no_bundles))
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read_enable = Array(Signal( name=f"bundle{i}_read_en") for i in range(self._no_bundles))
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for i in range(self._no_bundles):
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fifo = SyncFIFO(width=sample_width + bundle_bits + 1, depth=self.FIFO_DEPTH)
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setattr(m.submodules, f"receive_fifo{i}", fifo)
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m.d.comb += [
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*connect_stream_to_fifo(self.bundles_in[i], fifo),
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fifo.w_data[sample_width:].eq(self.bundles_in[i].channel_nr),
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fifo.w_data[-1].eq(self.bundles_in[i].last),
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bundle_ready[i] .eq(fifo.r_rdy),
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bundle_sample[i] .eq(fifo.r_data[:sample_width]),
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bundle_channel[i] .eq(fifo.r_data[sample_width:sample_width + bundle_bits]),
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self.levels[i] .eq(fifo.r_level),
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last[i].eq(fifo.r_data[-1]),
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fifo.r_en.eq(read_enable[i]),
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]
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current_bundle = Signal(range(self._no_bundles))
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first_bundle_channel = Signal(self._channel_bits)
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current_channel = Signal(self._channel_bits)
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last_bundle = Signal(self._bundle_channel_bits)
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m.d.comb += last_bundle.eq(current_bundle == (self._no_bundles - 1))
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m.d.comb += [
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self.current_bundle.eq(current_bundle),
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self.last_bundle.eq(last_bundle),
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]
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def handle_last_channel():
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with m.If(last_bundle):
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m.d.comb += self.channel_stream_out.last.eq(1)
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m.d.sync += [
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current_bundle.eq(0),
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first_bundle_channel.eq(0),
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]
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with m.Else():
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m.d.sync += [
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current_bundle.eq(current_bundle + 1),
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first_bundle_channel.eq(first_bundle_channel + self.no_channels_in[current_bundle])
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]
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with m.If(self.channel_stream_out.ready):
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# bundle is active (ie. ADAT cable plugged in and synced)
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with m.If(self.bundle_active_in[current_bundle]):
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with m.If(bundle_ready[current_bundle]):
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m.d.comb += [
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self.channel_stream_out.payload.eq(bundle_sample[current_bundle]),
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self.channel_stream_out.channel_nr.eq(first_bundle_channel + bundle_channel[current_bundle]),
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read_enable[current_bundle].eq(1),
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self.channel_stream_out.valid.eq(1),
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self.channel_stream_out.first.eq((current_bundle == 0) & (bundle_channel[current_bundle] == 0))
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]
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with m.If(last[current_bundle]):
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handle_last_channel()
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# bundle inactive (eg. no ADAT/SPDIF cable plugged in or not synced) => fill zeros
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with m.Else():
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last_channel = Signal()
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m.d.comb += [
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self.channel_stream_out.payload.eq(0),
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self.channel_stream_out.channel_nr.eq(first_bundle_channel + current_channel),
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self.channel_stream_out.valid.eq(1),
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self.channel_stream_out.first.eq(0),
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self.channel_stream_out.last.eq(0),
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last_channel.eq(current_channel == (self.no_channels_in[current_bundle] - 1))
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]
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m.d.sync += current_channel.eq(current_channel + 1)
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with m.If(last_channel):
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m.d.sync += current_channel.eq(0)
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handle_last_channel()
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return m
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class BundleMultiplexerTest(GatewareTestCase):
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FRAGMENT_UNDER_TEST = BundleMultiplexer
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FRAGMENT_ARGUMENTS = dict()
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def send_one_frame(self, bundle: int, sample: int, channel: int, wait=False):
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yield self.dut.bundles_in[bundle].channel_nr.eq(channel)
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yield self.dut.bundles_in[bundle].payload.eq(sample)
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yield self.dut.bundles_in[bundle].valid.eq(1)
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yield self.dut.bundles_in[bundle].first.eq(channel == 0)
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yield self.dut.bundles_in[bundle].last.eq(channel == 7)
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yield
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yield self.dut.bundles_in[bundle].valid.eq(0)
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if wait:
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yield
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def send_bundle_frame(self, bundle: int, sample: int):
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ch = list(range(self.dut.NO_CHANNELS_ADAT))
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first = ch[0:4]
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second = ch[4:]
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for channel in first:
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yield from self.send_one_frame(bundle, (sample << 8) + channel, channel)
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yield self.dut.bundles_in[bundle].valid.eq(0)
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yield
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yield
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for channel in second:
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yield from self.send_one_frame(bundle, (sample << 8) + channel, channel)
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@sync_test_case
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def test_smoke(self):
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dut = self.dut
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yield
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for bundle in range(4):
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yield self.dut.no_channels_in[bundle].eq(8)
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yield self.dut.bundle_active_in[bundle].eq(1)
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yield dut.channel_stream_out.ready.eq(1)
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yield
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for bundle in range(4):
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yield from self.send_bundle_frame(bundle, bundle)
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yield
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yield
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yield
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yield
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@sync_test_case
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def test_inactive_bundle(self):
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dut = self.dut
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yield
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yield dut.channel_stream_out.ready.eq(1)
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for bundle in range(4):
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yield self.dut.no_channels_in[bundle].eq(8)
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if (bundle != 2):
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yield dut.bundle_active_in[bundle].eq(1)
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yield
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for bundle in range(4):
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if bundle != 2:
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yield from self.send_bundle_frame(bundle, bundle)
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if bundle == 0:
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yield from self.advance_cycles(8)
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yield from self.advance_cycles(16)
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@sync_test_case
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def test_all_inactive(self):
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dut = self.dut
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yield
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yield dut.channel_stream_out.ready.eq(1)
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for bundle in range(4):
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yield self.dut.no_channels_in[bundle].eq(8)
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yield dut.bundle_active_in[bundle].eq(0)
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yield
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yield from self.advance_cycles(96)
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def send_all_bundle_frame(self):
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for channel in range(8):
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for bundle in range(4):
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yield self.dut.bundles_in[bundle].valid.eq(1)
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yield self.dut.bundles_in[bundle].channel_nr.eq(channel)
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yield self.dut.bundles_in[bundle].payload.eq((bundle << 16) | channel)
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yield self.dut.bundles_in[bundle].first.eq(channel == 0)
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yield self.dut.bundles_in[bundle].last.eq(channel == 7)
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yield
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for bundle in range(4):
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yield self.dut.bundles_in[bundle].valid.eq(0)
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yield
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@sync_test_case
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def test_all_sending(self):
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dut = self.dut
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yield
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yield dut.channel_stream_out.ready.eq(1)
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for bundle in range(4):
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yield self.dut.no_channels_in[bundle].eq(8)
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yield dut.bundle_active_in[bundle].eq(1)
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yield
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for _ in range(20):
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yield from self.send_all_bundle_frame()
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yield from self.advance_cycles(64)
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