567 lines
19 KiB
Python
567 lines
19 KiB
Python
from amaranth import *
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from amaranth.build import *
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from amaranth.lib.cdc import ResetSynchronizer
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from amaranth.lib.wiring import flipped
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from amlib.utils import SimpleClockDivider
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class ClockDomainGeneratorBase():
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NO_PHASE_SHIFT = 0
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def wire_up_reset(self, m, reset):
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m.submodules.reset_sync_fast = ResetSynchronizer(reset, domain="fast")
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m.submodules.reset_sync_usb = ResetSynchronizer(reset, domain="usb")
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m.submodules.reset_sync_sync = ResetSynchronizer(reset, domain="sync")
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m.submodules.reset_sync_dac = ResetSynchronizer(reset, domain="dac")
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m.submodules.reset_sync_adat = ResetSynchronizer(reset, domain="adat")
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class IntelCycloneIVClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
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ADAT_DIV_48k = 83
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ADAT_MULT_48k = 17
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ADAT_DIV_44_1k = 62
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ADAT_MULT_44_1k = 14
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DUTY_CYCLE = 50
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def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
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pass
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def elaborate(self, platform):
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m = Module()
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# Create our domains
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m.domains.usb = ClockDomain("usb")
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m.domains.sync = ClockDomain("sync")
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m.domains.fast = ClockDomain("fast")
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m.domains.adat = ClockDomain("adat")
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m.domains.dac = ClockDomain("dac")
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clk = flipped(platform.request(platform.default_clk))
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main_clocks = Signal(5)
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audio_clocks = Signal(4)
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fast_clock_48k = Signal()
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sys_locked = Signal()
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audio_locked = Signal()
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fast_locked = Signal()
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reset = Signal()
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m.submodules.mainpll = Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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# USB clock: 60MHz
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p_CLK0_DIVIDE_BY = 5,
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p_CLK0_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK0_MULTIPLY_BY = 6,
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p_CLK0_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# 44.1k ADAT Clock 11.2896 MHz = 44.1kHz * 256
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p_CLK1_DIVIDE_BY = self.ADAT_DIV_44_1k,
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p_CLK1_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK1_MULTIPLY_BY = self.ADAT_MULT_44_1k,
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p_CLK1_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# I2S DAC clock 44.1k = 3.072 MHz = 44.1kHz * 32 bit * 2 channels
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p_CLK2_DIVIDE_BY = self.ADAT_DIV_44_1k * 4,
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p_CLK2_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK2_MULTIPLY_BY = self.ADAT_MULT_44_1k,
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p_CLK2_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# ADAT sampling clock = 44.1kHz * 256 * 8 times oversampling
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p_CLK3_DIVIDE_BY = self.ADAT_DIV_44_1k,
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p_CLK3_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK3_MULTIPLY_BY = self.ADAT_MULT_44_1k * 8,
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p_CLK3_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# ADAT transmit domain clock = 44.1kHz * 5 output terminals
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p_CLK4_DIVIDE_BY = self.ADAT_DIV_44_1k,
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p_CLK4_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK4_MULTIPLY_BY = self.ADAT_MULT_44_1k * 5,
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p_CLK4_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# 50MHz = 20000 picoseconds
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p_INCLK0_INPUT_FREQUENCY = 20000,
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p_OPERATION_MODE = "NORMAL",
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# Drive our clock from the USB clock
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# coming from the USB clock pin of the USB3300
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i_inclk = clk,
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o_clk = main_clocks,
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o_locked = sys_locked,
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)
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m.submodules.audiopll = Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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# ADAT clock = 12.288 MHz = 48 kHz * 256
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p_CLK0_DIVIDE_BY = self.ADAT_DIV_48k,
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p_CLK0_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK0_MULTIPLY_BY = self.ADAT_MULT_48k,
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p_CLK0_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# I2S DAC clock 48k = 3.072 MHz = 48 kHz * 32 bit * 2 channels
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p_CLK1_DIVIDE_BY = self.ADAT_DIV_48k * 4,
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p_CLK1_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK1_MULTIPLY_BY = self.ADAT_MULT_48k,
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p_CLK1_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# ADAT sampling clock = 48 kHz * 256 * 8 times oversampling
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p_CLK2_DIVIDE_BY = self.ADAT_DIV_48k,
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p_CLK2_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK2_MULTIPLY_BY = self.ADAT_MULT_48k * 8,
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p_CLK2_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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# ADAT transmit domain clock = 48 kHz * 256 * 5 output terminals
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p_CLK3_DIVIDE_BY = self.ADAT_DIV_48k,
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p_CLK3_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK3_MULTIPLY_BY = self.ADAT_MULT_48k * 5,
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p_CLK3_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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p_INCLK0_INPUT_FREQUENCY = 16667,
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p_OPERATION_MODE = "NORMAL",
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i_inclk = main_clocks[0],
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o_clk = audio_clocks,
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o_locked = audio_locked,
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)
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m.submodules.fastpll = Instance("ALTPLL",
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p_BANDWIDTH_TYPE = "AUTO",
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# ADAT sampling clock = 48 kHz * 256 * 8 times oversampling
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p_CLK0_DIVIDE_BY = 1,
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p_CLK0_DUTY_CYCLE = self.DUTY_CYCLE,
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p_CLK0_MULTIPLY_BY = platform.fast_multiplier,
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p_CLK0_PHASE_SHIFT = self.NO_PHASE_SHIFT,
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p_INCLK0_INPUT_FREQUENCY = 81395,
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p_OPERATION_MODE = "NORMAL",
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i_inclk = audio_clocks[0],
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o_clk = fast_clock_48k,
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o_locked = fast_locked,
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)
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m.d.comb += [
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reset.eq(~(sys_locked & audio_locked & fast_locked)),
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ClockSignal("fast").eq(fast_clock_48k),
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ClockSignal("usb") .eq(main_clocks[0]),
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ClockSignal("adat").eq(audio_clocks[0]),
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ClockSignal("dac").eq(audio_clocks[1]),
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ClockSignal("sync").eq(audio_clocks[3]),
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]
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self.wire_up_reset(m, reset)
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return m
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class IntelCycloneVClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
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def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
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pass
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def elaborate(self, platform):
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m = Module()
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# Create our domains
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# usb: USB clock: 60MHz
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# adat: ADAT clock = 12.288 MHz = 48 kHz * 256
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# dac: I2S DAC clock 48k = 3.072 MHz = 48 kHz * 32 bit * 2 channels
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# sync: ADAT transmit domain clock = 61.44 MHz = 48 kHz * 256 * 5 output terminals
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# fast: ADAT sampling clock = 98.304 MHz = 48 kHz * 256 * 8 times oversampling
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m.domains.usb = ClockDomain("usb")
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m.domains.sync = ClockDomain("sync")
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m.domains.fast = ClockDomain("fast")
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m.domains.adat = ClockDomain("adat")
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m.domains.dac = ClockDomain("dac")
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clk = flipped(platform.request(platform.default_clk))
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main_clock = Signal()
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audio_clocks = Signal(4)
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sys_locked = Signal()
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audio_locked = Signal()
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reset = Signal()
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m.submodules.mainpll = Instance("altera_pll",
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p_pll_type="General",
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p_pll_subtype="General",
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p_fractional_vco_multiplier="false",
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p_operation_mode="normal",
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p_reference_clock_frequency="50.0 MHz",
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p_number_of_clocks="1",
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p_output_clock_frequency0="60.000000 MHz",
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# Drive our clock from the internal 50MHz clock
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i_refclk = clk,
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o_outclk = main_clock,
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o_locked = sys_locked
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)
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m.submodules.audiopll = Instance("altera_pll",
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p_pll_type="General",
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p_pll_subtype="General",
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p_fractional_vco_multiplier="true",
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p_operation_mode="normal",
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p_reference_clock_frequency="60.0 MHz",
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p_number_of_clocks="4",
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p_output_clock_frequency0="12.288000 MHz",
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p_output_clock_frequency1="3.072000 MHz",
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p_output_clock_frequency2="61.440000 MHz",
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p_output_clock_frequency3="98.304000 MHz",
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# Drive our clock from the mainpll
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i_refclk=main_clock,
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o_outclk=audio_clocks,
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o_locked=audio_locked
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)
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m.d.comb += [
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reset.eq(~(sys_locked & audio_locked)),
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ClockSignal("usb") .eq(main_clock),
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ClockSignal("adat").eq(audio_clocks[0]),
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ClockSignal("dac").eq(audio_clocks[1]),
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ClockSignal("sync").eq(audio_clocks[2]),
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ClockSignal("fast").eq(audio_clocks[3])
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]
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self.wire_up_reset(m, reset)
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return m
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class Xilinx7SeriesClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
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ADAT_DIV_48k = 83
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ADAT_MULT_48k = 17
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DUTY_CYCLE = 0.5
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def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
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pass
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def elaborate(self, platform):
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m = Module()
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# Create our domains
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m.domains.usb = ClockDomain("usb")
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m.domains.sync = ClockDomain("sync")
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m.domains.fast = ClockDomain("fast")
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m.domains.adat = ClockDomain("adat")
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m.domains.dac = ClockDomain("dac")
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clk = flipped(platform.request(platform.default_clk))
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main_clocks = Signal()
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audio_clocks = Signal(4)
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fast_clock_48k = Signal()
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sys_locked = Signal()
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audio_locked = Signal()
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fast_locked = Signal()
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reset = Signal()
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mainpll_feedback = Signal()
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audiopll_feedback = Signal()
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fastpll_feedback = Signal()
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m.submodules.mainpll = Instance("PLLE2_ADV",
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p_CLKIN1_PERIOD = 20,
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p_BANDWIDTH = "OPTIMIZED",
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p_COMPENSATION = "ZHOLD",
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p_STARTUP_WAIT = "FALSE",
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p_DIVCLK_DIVIDE = 1,
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p_CLKFBOUT_MULT = 30,
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p_CLKFBOUT_PHASE = self.NO_PHASE_SHIFT,
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# 60MHz
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p_CLKOUT0_DIVIDE = 25,
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p_CLKOUT0_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT0_DUTY_CYCLE = self.DUTY_CYCLE,
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i_CLKFBIN = mainpll_feedback,
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o_CLKFBOUT = mainpll_feedback,
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i_CLKIN1 = clk,
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o_CLKOUT0 = main_clocks,
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o_LOCKED = sys_locked,
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)
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m.submodules.audiopll = Instance("PLLE2_ADV",
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p_CLKIN1_PERIOD = 16.666,
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p_BANDWIDTH = "OPTIMIZED",
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p_COMPENSATION = "ZHOLD",
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p_STARTUP_WAIT = "FALSE",
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p_DIVCLK_DIVIDE = 1,
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p_CLKFBOUT_MULT = self.ADAT_MULT_48k,
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p_CLKFBOUT_PHASE = self.NO_PHASE_SHIFT,
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# ADAT clock = 12.288 MHz = 48 kHz * 256
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p_CLKOUT2_DIVIDE = self.ADAT_DIV_48k,
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p_CLKOUT2_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT2_DUTY_CYCLE = self.DUTY_CYCLE,
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# ADAT sampling clock = 48 kHz * 256 * 8 times oversampling
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p_CLKOUT0_DIVIDE = self.ADAT_DIV_48k / 8,
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p_CLKOUT0_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT0_DUTY_CYCLE = self.DUTY_CYCLE,
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# ADAT transmit domain clock = 48 kHz * 256 * 5 output terminals
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p_CLKOUT3_DIVIDE = self.ADAT_DIV_48k / 5,
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p_CLKOUT3_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT3_DUTY_CYCLE = self.DUTY_CYCLE,
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i_CLKFBIN = audiopll_feedback,
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o_CLKFBOUT = audiopll_feedback,
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i_CLKIN1 = main_clocks[0],
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o_CLKOUT0 = audio_clocks[2],
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o_CLKOUT2 = audio_clocks[0],
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o_CLKOUT3 = audio_clocks[3],
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o_LOCKED = audio_locked,
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)
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VCO_SCALER_FAST = 1
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m.submodules.fastpll = Instance("PLLE2_ADV",
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p_CLKIN1_PERIOD = 10.172,
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p_BANDWIDTH = "OPTIMIZED",
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p_COMPENSATION = "ZHOLD",
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p_STARTUP_WAIT = "FALSE",
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p_DIVCLK_DIVIDE = 1,
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p_CLKFBOUT_MULT = VCO_SCALER_FAST * platform.fast_multiplier,
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p_CLKFBOUT_PHASE = self.NO_PHASE_SHIFT,
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# Fast clock = 48 kHz * 256 * 9
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p_CLKOUT0_DIVIDE = VCO_SCALER_FAST,
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p_CLKOUT0_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT0_DUTY_CYCLE = self.DUTY_CYCLE,
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# I2S DAC clock 48k = 3.072 MHz = 48 kHz * 32 bit * 2 channels
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p_CLKOUT1_DIVIDE = VCO_SCALER_FAST * platform.fast_multiplier * 4,
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p_CLKOUT1_PHASE = self.NO_PHASE_SHIFT,
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p_CLKOUT1_DUTY_CYCLE = self.DUTY_CYCLE,
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i_CLKFBIN = fastpll_feedback,
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o_CLKFBOUT = fastpll_feedback,
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i_CLKIN1 = audio_clocks[2],
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o_CLKOUT0 = fast_clock_48k,
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o_CLKOUT1 = audio_clocks[1],
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o_LOCKED = fast_locked,
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)
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m.d.comb += [
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reset.eq(~(sys_locked & audio_locked & fast_locked)),
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ClockSignal("fast").eq(fast_clock_48k),
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ClockSignal("usb") .eq(main_clocks[0]),
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ClockSignal("adat").eq(audio_clocks[0]),
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ClockSignal("dac").eq(audio_clocks[1]),
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ClockSignal("sync").eq(audio_clocks[3]),
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]
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self.wire_up_reset(m, reset)
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return m
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class ColorlightDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
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""" Clock generator for the Colorlight I5 board. """
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FastDomainDivider = 7
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FastClockFreq = 25e6 * 29 / FastDomainDivider
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def __init__(self, clock_frequencies=None):
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pass
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def elaborate(self, platform):
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m = Module()
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# Create our domains.
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m.domains.sync = ClockDomain("sync")
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m.domains.usb = ClockDomain("usb")
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m.domains.fast = ClockDomain("fast")
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m.domains.adat = ClockDomain("adat")
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m.domains.dac = ClockDomain("dac")
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# Grab our clock and global reset signals.
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clk25 = flipped(platform.request(platform.default_clk))
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main_clocks = Signal(5)
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audio_clocks = Signal(4)
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fast_clock_48k = Signal()
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main_locked = Signal()
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audio_locked = Signal()
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fast_locked = Signal()
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reset = Signal()
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# USB PLL
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main_feedback = Signal()
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m.submodules.main_pll = Instance("EHXPLLL",
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# Status.
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o_LOCK=main_locked,
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# PLL parameters...
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p_PLLRST_ENA="DISABLED",
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p_INTFB_WAKE="DISABLED",
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p_STDBY_ENABLE="DISABLED",
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p_DPHASE_SOURCE="DISABLED",
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p_OUTDIVIDER_MUXA="DIVA",
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p_OUTDIVIDER_MUXB="DIVB",
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p_OUTDIVIDER_MUXC="DIVC",
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p_OUTDIVIDER_MUXD="DIVD",
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# 60 MHz
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p_CLKI_DIV = 5,
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p_CLKOP_ENABLE = "ENABLED",
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p_CLKOP_DIV = 10,
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p_CLKOP_CPHASE = 15,
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p_CLKOP_FPHASE = 0,
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p_FEEDBK_PATH = "CLKOP",
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p_CLKFB_DIV = 12,
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# Clock in.
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i_CLKI=clk25,
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# Internal feedback.
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i_CLKFB=main_feedback,
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# Control signals.
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i_RST=reset,
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i_PHASESEL0=0,
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i_PHASESEL1=0,
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i_PHASEDIR=1,
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i_PHASESTEP=1,
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i_PHASELOADREG=1,
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i_STDBY=0,
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i_PLLWAKESYNC=0,
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# Output Enables.
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i_ENCLKOP=0,
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i_ENCLKOS=0,
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# Generated clock outputs.
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o_CLKOP=main_feedback,
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# Synthesis attributes.
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a_FREQUENCY_PIN_CLKI="25",
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a_FREQUENCY_PIN_CLKOP="60",
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a_ICP_CURRENT="6",
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a_LPF_RESISTOR="16",
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a_MFG_ENABLE_FILTEROPAMP="1",
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a_MFG_GMCREF_SEL="2"
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)
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audio_feedback = Signal()
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audio_locked = Signal()
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m.submodules.audio_pll = Instance("EHXPLLL",
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# Status.
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o_LOCK=audio_locked,
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# PLL parameters...
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p_PLLRST_ENA="DISABLED",
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p_INTFB_WAKE="DISABLED",
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p_STDBY_ENABLE="DISABLED",
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p_DPHASE_SOURCE="DISABLED",
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p_OUTDIVIDER_MUXA="DIVA",
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p_OUTDIVIDER_MUXB="DIVB",
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|
p_OUTDIVIDER_MUXC="DIVC",
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|
p_OUTDIVIDER_MUXD="DIVD",
|
|
|
|
# 25MHz * 29 = 725 MHz PLL freqency
|
|
p_CLKI_DIV = 1,
|
|
p_CLKOP_ENABLE = "ENABLED",
|
|
p_CLKOP_DIV = 29,
|
|
p_CLKOP_CPHASE = 0,
|
|
p_CLKOP_FPHASE = 0,
|
|
|
|
# 12.288 MHz = 725 MHz / 59
|
|
p_CLKOS_ENABLE = "ENABLED",
|
|
p_CLKOS_DIV = 59,
|
|
p_CLKOS_CPHASE = 0,
|
|
p_CLKOS_FPHASE = 0,
|
|
|
|
# fast domain clock
|
|
p_CLKOS3_ENABLE = "ENABLED",
|
|
p_CLKOS3_DIV = self.FastDomainDivider,
|
|
p_CLKOS3_CPHASE = 0,
|
|
p_CLKOS3_FPHASE = 0,
|
|
|
|
p_FEEDBK_PATH = "CLKOP",
|
|
p_CLKFB_DIV = 1,
|
|
|
|
# Clock in.
|
|
i_CLKI=clk25,
|
|
|
|
# Internal feedback.
|
|
i_CLKFB=audio_feedback,
|
|
|
|
# Control signals.
|
|
i_RST=reset,
|
|
i_PHASESEL0=0,
|
|
i_PHASESEL1=0,
|
|
i_PHASEDIR=1,
|
|
i_PHASESTEP=1,
|
|
i_PHASELOADREG=1,
|
|
i_STDBY=0,
|
|
i_PLLWAKESYNC=0,
|
|
|
|
# Output Enables.
|
|
i_ENCLKOP=0,
|
|
i_ENCLKOS=0,
|
|
i_ENCLKOS3=0,
|
|
|
|
# Generated clock outputs.
|
|
o_CLKOP=audio_feedback,
|
|
o_CLKOS=ClockSignal("adat"),
|
|
o_CLKOS3=ClockSignal("fast"),
|
|
|
|
# Synthesis attributes.
|
|
a_FREQUENCY_PIN_CLKI="25",
|
|
a_FREQUENCY_PIN_CLKOS="12.288",
|
|
|
|
a_ICP_CURRENT="6",
|
|
a_LPF_RESISTOR="16",
|
|
a_MFG_ENABLE_FILTEROPAMP="1",
|
|
a_MFG_GMCREF_SEL="2"
|
|
)
|
|
|
|
debug0 = platform.request("debug", 0)
|
|
debug1 = platform.request("debug", 1)
|
|
debug2 = platform.request("debug", 2)
|
|
debug3 = platform.request("debug", 3)
|
|
|
|
m.submodules.bclk_div = clk_div = DomainRenamer("adat")(SimpleClockDivider(4))
|
|
|
|
reset = Signal()
|
|
# Control our resets.
|
|
m.d.comb += [
|
|
ClockSignal("usb") .eq(main_feedback),
|
|
ClockSignal("sync") .eq(ClockSignal("usb")),
|
|
ClockSignal("dac") .eq(clk_div.clock_out),
|
|
clk_div.clock_enable_in.eq(1),
|
|
|
|
reset.eq(~(main_locked & audio_locked)),
|
|
|
|
debug0.eq(ClockSignal("usb")),
|
|
debug1.eq(ClockSignal("adat")),
|
|
debug2.eq(ClockSignal("fast")),
|
|
debug3.eq(reset),
|
|
|
|
]
|
|
|
|
self.wire_up_reset(m, reset)
|
|
|
|
return m
|